verilog HDLBits刷题[Counters]“Exams/ece241 ”---Counter 1000

一、题目From a 1000 Hz clock, derive a 1 Hz signal, calledOneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, theOneHertzsignal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).The following BCD counter is provided for you.Enablemust be high for the counter to run.Resetis synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.module bcdcount ( input clk, input reset, input enable, output reg [3:0] Q );Module Declarationmodule top_module ( input clk, input reset, output OneHertz, output [2:0] c_enable );二、分析子模块为10进制BCD码计数每个计数器从0计数到9.将1000Hz分频为1Hz可以使用三个计数器分别计数个位十位百位个位计满了十位开始计数十位也计满了后百位开始计数。每个计数器的使能表示该计数器开启计数。三、代码实现module top_module ( input clk, input reset, output OneHertz, output [2:0] c_enable ); // wire [3:0] q0,q1,q2; assign c_enable{q14d9q04d9,q04d9,1b1}; assign OneHertz {q2 4d9 q1 4d9 q0 4d9}; bcdcount counter0 (clk, reset, c_enable[0],q0); bcdcount counter1 (clk, reset, c_enable[1],q1); bcdcount counter2 (clk, reset, c_enable[2],q2); endmodule 或者 module top_module ( input clk, input reset, output OneHertz, output [2:0] c_enable ); // wire [3:0]cnt0,cnt1,cnt2;//分别是个位十位百位的计算器 bcdcount counter0 (clk, reset, c_enable[0],cnt0); bcdcount counter1 (clk, reset, c_enable[1],cnt1); bcdcount counter2 (clk, reset, c_enable[2],cnt2); assign c_enable[0]1b1;//个位的计算器一直在运行 assign c_enable[1](cnt04d9)c_enable[0];//个位计满并且还在计数时十位的计数器开始运行 assign c_enable[2](cnt04d9cnt14d9)c_enable[1];//个位数计满、十位计满并且还在计数时百位的计数器开始运行 assign OneHertz(cnt04d9cnt14d9cnt24d9);//个十百位都计满9即999则为1Hz endmodule四、时序